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| ? 1 ? e03203-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. CXD2932AR-2 144 pin lqfp (plastic) gps base band lsi description the CXD2932AR-2 is a dedicated lsi for the gps (global positioning system) satellite-based position measurement system. this lsi contains a 32-bit risc cpu, satellite tracking circuit, 2m-bit mask rom, ram, uart, interval timer, and others. this lsi, used together with the rf lsi, enables the configuration of a 2-chip system capable of measuring its position anywhere on the globe. features ? 16-channel gps receiver capable of simultaneously receiving 16 satellites supports differential gps ? conforms to rtcm sc-104 ver. 2.1 ? supports darc all-in-view measurement timer supporting gps time 32-bit risc cpu 256k-byte program rom 40k-byte ram power management function 1pps supported 2-channel uart 4-channel interval timer 16-bit general-purpose i/o port 12-bit successive approximation system a/d converter (4-channel analog switch) structure silicon gate cmos ic absolute maximum ratings supply voltage v dd v ss ? 0.5 to 4.6 v input voltage v i v ss ? 0.5 to v dd + 0.5 v output voltage v o v ss ? 0.5 to v dd + 0.5 v operating temperature topr ?40 to +85 c storage temperature tstg ?50 to +150 c recommended operating conditions supply voltage v dd 3.0 to 3.6 v operating temperature topr ?40 to +85 c input/output pin capacitance input capacitance c in 9 (max.) pf output capacitance c out 11 (max.) pf i/o capacitance c i/o 11 (max.) pf
? 2 ? CXD2932AR-2 performance 16-channel gps receiver 32-bit risc cpu receiver frequency: 1575.42mhz (l1 band, ca code) reception sensitivity tracking sensitivity: ?145dbm or less (typ.) when using the antenna of 25dbi, nf = 2db and the rf amplifier with the 25db gain for the rf block ? reference data using the sony's reference board. this value is not guaranteed, depending on the conditions. time to first fix (time until initial measurement after power-on) cold start (without both ephemeris and almanac): 27 to 58s warm start (without ephemeris with almanac): 23 to 45s hot start (with both ephemeris and almanac): 6 to 17s ? reference data with elevation angle of 5 or more and no interception environment on june, 2002. positioning time with 90% possibility. these values are not guaranteed, depending on the conditions. positioning accuracy 2drms: approx. 5m ? reference data with elevation angle of 5 or more and no interception environment on june, 2002. this value is not guaranteed, depending on the conditions. measurement data update time: 1s communication format: sony binary nmea-0183 customized nmea (9600bps) all-in-view ? 3 ? CXD2932AR-2 block diagram system (sys_reg) 32k-timer (itu32k) usb/drv (usb) port (port) decoder (decoder) arm-core (a7tdmi) arm7tdmi sram: 40kb (dmem_40kb) rom: 256kb (imem_m) arbiter (arbiter) apb-bridge (apbif) tic (tic) bus-i/f (smi) addr: 20 bit data: 32 bit addr: 32 bit data: 32 bit addr: 20 bit data: 32 bit 9 to 18mhz (arm) 18mhz (tcxo) 6mhz (usb) clkgen (clkgen) apb ahb tap-ctl (dftc6) jtag (arm-core) bist (sram) scan jtag tcxo/xtcxo (osc) xint[1:0] ifi/ifo(osc) clki/clko (osc) rxd[1:0] txd[1:0] usb-i/f port[15:0] ea[19:0] ed[31:0] ahb: amba high performance bus apb: amba peripheral bus tic: test interface controller refck xcs[3:0] xoe xwe[3:0] clkout a/d xpwrs xrs xgbe xromi romw clks[2:0] test[1:0] uart: 2ch (duart) timer: 3ch (tmitu) ssd1: 17ch (ssd1) interrupt (int_cntl) ? 4 ? CXD2932AR-2 pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 133 134 135 136 137 138 139 140 141 142 143 144 121 122 123 124 125 126 127 128 129 130 131 132 109 110 111 112 113 114 115 116 117 118 119 120 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 96 97 98 99 100 101 102 103 104 105 106 107 108 91 92 93 94 95 v ss 8 ea14 ea13 ea12 ea11 ea10 v dd 7 ea9 ea6 ea8 ea7 ea5 v ss 7 ea4 ea3 ea2 ea1 ea0 v dd 6 ed31 ed28 ed30 ed29 ed27 port1 port0 xcs3 xcs2 xcs1 xcs0 v dd 8 ea19 ea16 ea18 ea17 ea15 v ss 6 ed26 ed25 ed24 ed23 ed22 v dd 5 ed21 ed20 ed19 ed18 ed17 v ss 5 ed16 ed15 ed14 ed13 ed12 v dd 4 ed11 ed10 ed9 ed8 ed7 v ss 4 ed6 ed5 ed4 ed3 ed2 v dd 3 ed1 ed0 romw xromi xoe v ss 3 xwe3 xwe2 xwe1 xwe0 xint1 v dd 2 xint0 xrs xpwrs gbe clkout v ss 2 clko clki clks2 clks1 clks0 v dd 1 xtcxo tcxo v ss 1 avs3 usbdp usbdm avd3 avs1 avd1 avs2 vrt vrb vin3 vin2 vin1 vin0 avd2 v ss 9 port2 port3 port4 port5 port6 port7 v dd 9 port8 port9 port10 port11 port12 port13 v ss 10 port14 port15 txd0 rxd0 txd1 rxd1 v dd 10 ifi ifo test0 test1 ccki ccko v ss 11 refck trst tck tdi tdo tms v dd 11 ? 5 ? CXD2932AR-2 pin description pin no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 symbol v ss 9 port2 port3 port4 port5 port6 port7 v dd 9 port8 port9 port10 port11 port12 port13 v ss 10 port14 port15 txd0 rxd0 txd1 rxd1 v dd 10 ifi ifo test0 test1 ccki ccko v ss 11 refck trst tck tdi tdo tms v dd 11 avd2 i/o ? i/o/z i/o/z i/o/z i/o/z i/o/z i/o/z ? i/o/z i/o/z i/o/z i/o/z i/o/z i/o/z ? i/o/z i/o/z o/z i o/z i ? i o i i i o ? i i i i o/z i ? ? description v ss i/o port 2 (see the application circuit for setting.) i/o port 3 (see the application circuit for setting.) i/o port 4 (see the application circuit for setting.) i/o port 5 (see the application circuit for setting.) i/o port 6 (see the application circuit for setting.) i/o port 7 (see the application circuit for setting.) v dd i/o port 8 (see the application circuit for setting.) i/o port 9 (see the application circuit for setting.) i/o port 10 (see the application circuit for setting.) i/o port 11 (see the application circuit for setting.) i/o port 12 (see the application circuit for setting.) i/o port 13 (see the application circuit for setting.) v ss i/o port 14 i/o port 15 uart transmission data (ch0) uart reception data (ch0) uart transmission data (ch1) uart reception data (ch1) v dd if signal binary conversion circuit test (low level fixed) test (low level fixed) timer oscillation circuit (32.768khz 100ppm) v ss test (low level fixed) test (open) test (open) test (open) test test (open) v dd a/d converter v dd ? 6 ? CXD2932AR-2 pin no. 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 symbol vin0 vin1 vin2 vin3 vrb vrt avs2 avd1 avs1 avd3 usbdm usbdp avs3 v ss 1 tcxo xtcxo v dd 1 clks0 clks1 clks2 clki clko v ss 2 clkout gbe xpwrs xrs xint0 v dd 2 xint1 xwe0 xwe1 xwe2 xwe3 v ss 3 xoe xromi i/o i i i i i i ? ? ? ? i/o/z i/o/z ? ? i o ? i i i i o ? o/z i i i i ? i o o o o ? o i description analog input (ch0) analog input (ch1) analog input (ch2) analog input (ch3) reference input (bottom) reference input (top) a/d converter v ss pll v dd pll v ss usb v dd usb data + (not supported in this ic. pull down with 15k ? ) usb data ? (not supported in this ic. pull down with 15k ? ) usb v ss v ss tcxo crystal oscillator (18.414mhz 3ppm) v dd cpu clock selection (clks2, clks1, clks0) = (0, 0, 1): 18.414mhz (tcxo) (clks2, clks1, clks0) = (0, 1, 0): 27.671mhz (tcxo 1.5) cpu clock oscillator v ss 1pps output external bus enable (h-active) oscillator enable (h-active) reset (l-active) external interruption 0 (l-active) v dd external interruption 1 (l-active) external expansion write signal 0 external expansion write signal 1 external expansion write signal 2 external expansion write signal 3 v ss external expansion read signal program area selection (low: internal / high: external) ? 7 ? CXD2932AR-2 pin no. symbol i/o description 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 romw ed0 ed1 v dd 3 ed2 ed3 ed4 ed5 ed6 v ss 4 ed7 ed8 ed9 ed10 ed11 v dd 4 ed12 ed13 ed14 ed15 ed16 v ss 5 ed17 ed18 ed19 ed20 ed21 v dd 5 ed22 ed23 ed24 ed25 ed26 v ss 6 ed27 ed28 ed29 i i/o/z i/o/z ? i/o/z i/o/z i/o/z i/o/z i/o/z ? i/o/z i/o/z i/o/z i/o/z i/o/z ? i/o/z i/o/z i/o/z i/o/z i/o/z ? i/o/z i/o/z i/o/z i/o/z i/o/z ? i/o/z i/o/z i/o/z i/o/z i/o/z ? i/o/z i/o/z i/o/z test (low level fixed) external expansion data 0 external expansion data 1 v dd external expansion data 2 external expansion data 3 external expansion data 4 external expansion data 5 external expansion data 6 v ss external expansion data 7 external expansion data 8 external expansion data 9 external expansion data 10 external expansion data 11 v dd external expansion data 12 external expansion data 13 external expansion data 14 external expansion data 15 external expansion data 16 v ss external expansion data 17 external expansion data 18 external expansion data 19 external expansion data 20 external expansion data 21 v dd external expansion data 22 external expansion data 23 external expansion data 24 external expansion data 25 external expansion data 26 v ss external expansion data 27 external expansion data 28 external expansion data 29 ? 8 ? CXD2932AR-2 pin no. 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 symbol ed30 ed31 v dd 6 ea0 ea1 ea2 ea3 ea4 v ss 7 ea5 ea6 ea7 ea8 ea9 v dd 7 ea10 ea11 ea12 ea13 ea14 v ss 8 ea15 ea16 ea17 ea18 ea19 v dd 8 xcs0 xcs1 xcs2 xcs3 port0 port1 i/o i/o/z i/o/z ? o/z o/z o/z o/z o/z ? o/z o/z o/z o/z o/z ? o/z o/z o/z o/z o/z ? o/z o/z o/z o/z o/z ? o o o o i/o/z i/o/z description external expansion data 30 external expansion data 31 v dd external expansion address 0 external expansion address 1 external expansion address 2 external expansion address 3 external expansion address 4 v ss external expansion address 5 external expansion address 6 external expansion address 7 external expansion address 8 external expansion address 9 v dd external expansion address 10 external expansion address 11 external expansion address 12 external expansion address 13 external expansion address 14 v ss external expansion address 15 external expansion address 16 external expansion address 17 external expansion address 18 external expansion address 19 v dd external expansion chip select 0 external expansion chip select 1 external expansion chip select 2 external expansion chip select 3 i/o port 0 (see the application circuit for setting.) i/o port 1 (see the application circuit for setting.) ? 9 ? CXD2932AR-2 analog characteristics (1) a/d converter characteristics (avd = 3.0 to 3.6v, topr = ?40 to +85c) item resolution channel differential linearity error (dle) integral linearity error (ile) sampling time conversion time reference power (top) reference power (bottom) analog input power current consumption symbol conditions avd = 3.0v f = 18.414mhz avd = 3.0v min. ?1.0 ?1.0 5 15 vrb 0 vrb ty p. 4 5 max. 12 +1.0 +1.0 avd vrt vrt unit bit ch lsb lsb s s v v v ma vrt vrb vin0-3 applicable pins ? 1 ? 2 ? 3 applicable pins ? 1 pin 43 ? 2 pin 42 ? 3 pins 38 to 41 (2) usb characteristics (avd = 3.0 to 3.6v, topr = ?40 to +85c) item output impedance output voltage (low) output voltage (high) data rise delay time data fall delay time data delay time ratio crossover voltage current consumption (during operation) current consumption (during suspension) symbol conditions ? rl = 1.5k ? to 3.6v rl = 1.5k ? to gnd cl = 50pf cl = 350pf cl = 50pf cl = 350pf cl = 50pf or 350pf cl = 50pf or 350pf cl = 50pf and v cc = 3.6v v cc = 3.6v min. 28 ? 2.8 75 ? 75 0.8 1.3 ? ? typ. max. 43 0.3 3.6 ? 300 ? 300 1.2 2.0 20 2 unit ? v v ns ns ns ns ? v ma ma zdrv v ol v oh tr tf tr/tf vcrs ica icb applicable pins pins 48, 49 ? 10 ? CXD2932AR-2 dc characteristics (vdd = 3.0 to 3.6v, topr = ?40 to +85c) item high level low level high level low level high level low level high level low level high level low level high level low level high level low level when gps measurement when external timer used when internal timer used input voltage (1) (coms level) input voltage (2) (5v interface) input voltage (3) (schmitt) output voltage (1) output voltage (2) output voltage (3) output voltage (4) (5v interface) current consumption (during normal operation) current consumption (in backup mode) v ih v il v ih v il v ih v il v oh v ol v oh v ol v oh v ol v oh v ol icur istb1 istb2 i oh = ?4.0ma i ol = 4.0ma i oh = ?8.0ma i ol = 8.0ma i oh = ?2.0ma i ol = 8.0ma i oh = ?2.0ma i ol = 4.0ma 3.0v, 18.414mhz 3.0v, 27.671mhz 3.0v 3.0v 0.7v dd 0.7v dd 0.7v dd v dd ? 0.4 v dd ? 0.4 v dd ? 0.8 v dd ? 0.8 0.2v dd 5.5 0.2v dd 0.2v dd 0.4 0.4 0.4 0.4 60 100 63 75 3 5 v v v v v v v v v v v v v v ma ma a a ? 1 ? 2 ? 3 ? 4 ? 5 ? 6 ? 7 symbol conditions min. typ. max. unit applicable pins applicable pins ? 1 pins 25, 26, 31 to 33, 35, 55 to 57, 74 to 77, 79 to 83, 85 to 89, 91 to 95, 97 to 101, 103 to 107, 109 to 113 ? 2 pins 2 to 7, 9 to 14, 16, 17, 19, 21, 30, 62, 65, 67, 143, 144 (use the resistor of 4.7k ? or less when the pull-down is performed.) ? 3 pins 63, 64 ? 4 pins 34, 61 ? 5 pins115 to 119, 121 to 125, 133 to 137, 139 to 142, 68 to 71, 73, 76, 77, 79 to 83, 85 to 89, 91 to 95, 97 to 101, 103 to 107, 109 to 113 ? 6 pins 2 to 7, 9 to 14, 16, 17, 143, 144 ? 7 pins 18, 20 ? 11 ? CXD2932AR-2 item read cycle time (0wait) ? 1 read cycle time (1wait) ? 1 read cycle time (2wait) ? 1 read cycle time (3wait) ? 1 address delay time read signal fall delay time read signal rise delay time read data setup time read data hold time min. 0 2 2 22 ty p. 54 108 162 216 max. 4 10 10 0 unit ns ns ns ns ns ns ns ns ns symbol trcy0 trcy1 trcy2 trcy3 tca tcfo tcro tds tdh ac characteristics (1) external memory read timing (v dd = 3.0 to 3.6v, cl = 40pf, topr = ?40 to +85c, cpu clock = 18.4mips) ? 1 0wait (normal), 1 to 3wait (settable according to the program) xcs ea xoe ed tca tcfo tsys ? (1 to 4) tsys tds tdh tca trcy0 to 3 tcro ? tsys: cpu clock cycle ? 12 ? CXD2932AR-2 item write cycle time (0wait) ? 1 write cycle time (1wait) ? 1 write cycle time (2wait) ? 1 write cycle time (3wait) ? 1 address delay time write signal fall delay time write signal rise delay time write data setup time write data hold time min. 0 2 2 2 2 ty p. 162 216 270 324 max. 4 6 8 15 10 unit ns ns ns ns ns ns ns ns ns symbol twcy0 twcy1 twcy2 twcy3 tca tcfo tcro tds tdh (2) external memory write timing (v dd = 3.0 to 3.6v, cl = 40pf, topr = ?40 to +85c, cpu clock = 18.4mips) ? 1 0wait (normal), 1 to 3wait (settable according to the program) xcs ea xwe ed tca tcfo tsys tsys ? (1 to 4) tds tca twcy0 to 3 tcro tsys' tdh ? tsys: cpu clock cycle ? 13 ? CXD2932AR-2 backup mode when the power supply of the gps receiver system is off (xpwrs = low: the external pull-down is necessary) and the reset state (xrs = low) is established, the device goes into the low power consumption state (backup mode) where the all oscillators except for the timer stop. the whole internal memory status at this time is retained and the hot start/warm start can be achieved. in order to cancel this mode, set the xrs pin to high after xpwrs is set to high and then the oscillation stabilization time and the pll lock-in time are waited. (normal operation / reset : v dd = 3.0 to 3.6v, backup mode : v dd = 2.0 to 3.6v) osc output xpwrs xrs oscillation stabilization time pll lock-in time (max. 1.0ms) backup reset normal normal hi-z output ed[31:0], ea[19:0] port[15:0] xcs[3:0], xwe[3:0], xoe, xtcxo txd[1:0], clkout low output high output pull-down output ? 14 ? CXD2932AR-2 initialization setting the device initialization is started by setting the reset pin (xrs) to low level. the timing should satisfy the conditions noted below. (1) during power-on (v dd = 3.0 to 3.6v, topr = ?40 to +85c) xpwrs should rise simultaneously with the power supply. xrs should rise 100ms or more after the power supply and xpwrs have risen. v dd v ss xrs power supply xpwrs v dd /2 100ms or more (2) initialization during operation (v dd = 3.0 to 3.6v, topr = ?40 to +85c) the internal registers can be initialized during operation by setting the xrs signal to low level for 100s or more. keep the xpwrs signal at high level at this time. (the internal memory value is held.) v dd v ss xrs power supply xpwrs v dd /2 1s or more ? 15 ? CXD2932AR-2 application notes the constants shown in the circuits below are the examples, and do not guarantee the circuit operation. (1) tcxo input (a) when inputting the binary-converted signal the tcxo input signal should be 18.414mhz 3ppm. (b) when performing the self-oscillation with the tcxo and xtcxo pins the tcxo input signal should be 18.414mhz 3ppm. for inputting the signal which is not binary converted, the signal should go through the dc cut capacitor. (2) cpu clock generation (a) cpu clock selector the clks2, clks1 and clks0 pins are used to select that the tcxo clock is used or that the self- oscillation is performed with the clki and clko pins. set the clki pin to low when the tcxo clock is used. (clks[2:0] = 001: recommendation) (b) when performing the self-oscillation with the clki and clko pins the crystal oscillator frequency should be within the values shown above. 52 53 input open 52 53 0.01f 1m ? input 58 59 22pf 22pf 1m ? 12 to 27mhz clks[2:0] 001 010 101 110 clki, clko ? ? 18 to 27mhz 12 to 18mhz cpu frequency tcxo 1.0 (18.414mhz) tcxo 1.5 (27.671mhz) clki 1.0 (18 to 27mhz) clki 1.5 (18 to 27mhz) ? 16 ? CXD2932AR-2 (3) timer clock setting when using the real-time clock (rtc) circuit in the device, connect the crystal oscillator of 32.768khz 100ppm to the ccki and ccko pins. when using the external rtc circuit, set the ccki pin to the low level. see the port setting for the rtc internal/external selection. (4) if signal input this device's if signal supports only 1.023mhz. when the signal which is not binary-converted is input, the signal should go through the dc cut capacitor. (5) serial input/output communication system see the corresponding data sheet for communication because the communication specification differs according to the communication format. see the port setting for the communication format selection. the transmission data (txd0 and txd1) amplitude is 0.4v or less for the low level and v dd ? 0.4v or more for the high level. when the lsi and others connected to this operate at 5v and the cmos level input is used, convert 3v to 5v for input. 27 28 22pf 22pf 32.768khz 100ppm 23 24 0.01f input 1m ? ? 17 ? CXD2932AR-2 (6) port setting when the power turns on or initialization setting is performed by the reset input, the system starts operation according to the selected port setting. perform initialization after the setting is changed because the setting can not be changed during operation. i/o 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 description i i i i i i i i i i i i i i i i i i i i i i o o o i o i o i/o o o port test pin (low = normal mode) communication format selection port[2:1] = (00: sony binary, 01: nmea4800, 10: nmea9600, 11: unused) rtc selection (high = internal / low = external) test pin (high = normal mode) test pin (low = normal mode) unused unused unused antenna sense (low = disable / high = enable) antenna shutdown (high = cut) test pin (low = normal mode) unused rtc sio (leave open when the internal rtc is selected.) rtc scl (leave open when the internal rtc is selected.) rtc ce (leave open when the internal rtc is selected.) for reset for operation (7) a/d setting the antenna sense function can be realized by connecting the antenna power supply of the gps receiver to the a/d channel pins shown below. see the application circuit for the resistance value and others. see the port setting for the antenna sense function disable/enable selection. i/o 0 1 2 3 description i i i i i i i i vin antenna power supply (before current value detection resistor) antenna power supply (after current value detection resistor) test pin (low level fixed) test pin (low level fixed) for reset for operation ? 18 ? CXD2932AR-2 application circuit 15k v ss 8 ea14 ea13 ea12 ea11 ea10 v dd 7 ea9 ea6 ea8 ea7 ea5 v ss 7 ea4 ea3 ea2 ea1 ea0 v dd 6 ed31 ed28 ed30 ed29 ed27 port1 port0 xcs3 xcs2 xcs1 xcs0 v dd 8 ea19 ea16 ea18 ea17 ea15 v s s 6 ed26 ed25 ed24 ed23 ed 22 v d d 5 ed 21 ed20 ed19 ed18 ed17 v s s 5 ed 16 ed15 ed 14 ed13 ed12 v d d 4 ed11 ed10 ed9 ed8 ed7 v s s 4 ed6 ed5 ed4 ed3 ed2 v d d 3 ed1 ed0 r o m w xr o m i xo e v ss 3 xwe3 xwe2 xwe1 xwe0 xint1 v dd 2 xint0 xrs xpwrs gbe clkout v ss 2 clko clki clks2 clks1 clks0 v dd 1 xtcxo tcxo v ss 1 avs3 usbdp usbdm avd3 avs1 avd1 avs2 vrt vrb vin3 vin2 vin1 vin0 avd2 v s s 9 po r t2 po r t3 po r t4 po r t5 po r t6 po r t7 v d d 9 po r t8 po r t9 po r t10 po r t11 po r t12 po r t13 v s s 10 por t14 po r t15 txd0 rxd0 txd1 rxd 1 v d d 10 ifi ifo test 0 test 1 cc ki cck o v s s 11 r efc k trst tck tdi tdo tm s v d d 11 CXD2932AR-2 v s s sio sc l ce int o sco osci v d d cd gnd v dd out rn3112q291a gnd reset batt out max6364lut26 resetin v cc reset gnd txd0 tcxo (18.414mhz) rxd0 rxd1 if (1.023mhz) v dd (3.3v) 1pps a16 a12 a13 a14 a15 we i/o6 i/o8 i/o7 i/o5 gnd v dd i/o4 i/o3 i/o2 i/o1 ce a0 a3 a1 a2 a4 a5 a6 a7 oe ub lb i/o16 i/o15 i/o14 i/o13 gnd v dd i/o12 i/o11 i/o10 i/o9 nu a8 a9 a10 a11 a17 ea13 ea14 ea15 ea16 xwe1 ed23 ed22 ed21 ed19 ed18 ed17 ed16 xcs0 ea1 ea5 ea6 ea7 ea8 xoe ed31 ed30 ea9 ea10 ea11 ea12 ea13 ea17 ea4 ea2 0.1 4.7k 4.7k 4.7k 4.7k 1m 22p 22p 32.768k 32.768k 22p 22p 0.01 15k 1m 0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.01 0.1 47h 47h 0.1 v ss v dd v dd v ss 47k 10h 0.1 3.0v ea3 ed20 ed29 ed28 ed24 ed25 ed26 ed27 tc55v16256fti ? 19 ? CXD2932AR-2 package outline unit: mm sony code jeita code jedec code package structure package material lead treatment lead material package mass epoxy resin 42 / copper alloy lqfp-144p-l01 p-lqfp144-20x20-0.5 1.3 g 144pin lqfp (plastic) 0.1 0.05 (21.0) 0.5 0.15 0? to 10? detail a 1 36 37 72 73 108 109 144 b 0.5 m 0.08 1.7 max 1.4 0.1 a b 0.1 s s 22.0 0.2 20.0 0.1 s (0.125) 0.145 0.04 b = 0.22 0.05 (0.2) detail b : solder solder plating lead plating specifications item lead material copper alloy solder composition sn-bi bi:1-4wt% plating thickness 5-18m spec. sony corporation |
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